The new 128GB DRAM chip is designed for high-performance computing devices and servers. The South Korean firm worked with Intel for this new standard, and it works with the Intel Xeon platform.

It supports the new PCIe 5.0 standard (using x8 lanes) and offers data transfer bandwidth of up to 35Gbps. The new CXL standard now supports memory pooling. It binds multiple memory blocks on a server to create multiple memory pools. It allows hosts to dynamically allocate memory pools based on their needs and requirements, which increases overall efficiency and reduces operating costs.

Samsung has announced that it will start the mass production of CXL 2.0 DRAM chips later this year and offer them in various sizes to its clients for high-performance computing and servers. These chips can add more bandwidth and capacity to the main DRAM in a server, offering faster AI (Artificial Intelligence) and ML (Machine Learning) performance.

Samsung VP Jangseok Choi said, “As a member of the CXL Consortium Board of Directors, Samsung Electronics remains at the forefront of CXL technology. This breakthrough development underlines our commitment to expanding the CXL ecosystem even further through partnerships with data center, server, and chipset companies across the industry.“